Job Description

Digital ASIC Design Verification Engineer

Minneapolis, MN (onsite)

US Citizen or US Permanent Resident

Full-Time + Health Benefits + 401K Plan with profit sharing + PTO + Stock Option Plan

Duties and Responsibilities

• reviewing and editing target specifications as required for completeness and feasibility
• developing architectures and specifications for complex design blocks and SOCs
• implementing complex digital designs using reusable RTL methods (Verilog, VHDL, SystemVerilog)
• complex computational architectures and algorithms, such as multi-rate/DSP and µP design
• modern verification methods, including directed/constrained-random stimuli, assertions, TLM and UVM
• collaborative creation of comprehensive verification plans and coverage metrics
• multi-supply-domain and UPF methods
• constraining and synthesizing digital designs to target cell libraries
• static timing, power, and SI analyses of complex digital designs
• supporting place & route efforts, including P/G and floorplanning, timing and physical constraints, gated CTS, MCMM setups, back-annotation, timing closure, equivalence checking
• planning, implementing, and analyzing designs for DFT, test hooks, and scan/ATPG/JTAG/BIST, and supporting production test with ATE patterns (ATPG and functional) and timeset definitions
• proficiency with Synopsys EDA, including DC-Topo, VCS-MX, PrimeTime, Formality, TetraMAX
• proficiency with Mentor EDA, including Questa, ADMS, Tessent
• modern revision-control tools and best-practices in a collaborative, multi-site design community
• proficiency with UNIX/Linux including shell scripting, text utilities (e.g. sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting
• proficiency with Windows apps, including Word, Excel, PowerPoint, Visio, Project, PDF conversion

Requirements

• BSEE/MSEE or BSCS/MSCS or equivalent
• 7+ years of direct industry experience with ASIC and/or SoC design
• a strong background in RTL based digital IC design using Verilog/SystemVerilog
• proven track record of first-pass successes
• self-starter with the ability to assume leadership roles
• ability to work well in a diverse team environment
• willingess to mentor junior engineers
• experience with industry standard development tools and methodologies

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